Semiconductor memory devices which are made by semiconductor wafer processes are desired to be error-free in writing data into and reading data from their individual cells. When such a semiconductor memory device has a small memory capacity, it would not require much time to test the essential functions of the cells of the device. However, when such a semiconductor memory device has a large memory capacity (e.g., memory capacity of over 1 Mb (mega byte) which is commercially available now), it would require much time to test the entire cells of the device one by one.
In order to test the cells more efficiently, more reliably and faster, a multi-bit testing circuit has been devised. Such a high speed and high reliability testing circuit has not only improved the reliability of the memory device, but also reduced the testing time, as well as reducing the size of the cell. One example of such a semiconductor memory multi-bit testing circuit is illustrated in FIGS. 1A and 1B.
FIG. 1A represents the first sensing portion of the multi-bit testing circuit. As shown in FIG. 1A, the memory device includes a plurality of memory cells 1. Each cell is coupled to a pair of a bit line and a reference line. When the circuit operates under a normal operating mode, each of these pairs produces a signal S having values complementary to one another. Referring to FIG. 1A, the conventional multi-bit testing circuit includes a pair of first sense amplifiers 10A and 10B to sense and amplify the data output from the memory cells 1. The first sense amplifiers 10A and 10B further include a column selector (not shown) for selecting one or more columns from a plurality of columns YD0 . . . YDi associated with the first sense amplifier 10A and/or from a plurality of columns YDj . . . YDn associated with the first sense amplifier 10B.
The first sense amplifier 10A, when activated, provide, through a first signal path, outputs SA and SA and the first sense amplifier 10B provides, through a second signal path, outputs SB and SB likewise. These outputs are provided to a second sense amplifier 20 having a current mirror, as shown in the second sensing portion (i.e., FIG. 1B). This conventional multi-bit testing circuit operates under a normal operating mode or a multi-bit testing mode.
Under the normal operating mode, the column selector selects only one column from the columns YD0-YDi or YDj-YDn. For example, if the column selector selects one column (e.g., YD0) from the columns YD0 to YDi associated with the first sense amplifier 10A, the first sense amplifier 10A becomes activated and outputs complementing data signals as SA and SA. SA corresponds to the signal sensed from the bit line and SA from the reference line associated with the selected column. The first sense amplifier 10B, which is kept deactivated because none of its associated columns have been selected, outputs signals having a voltage corresponding to Vcc as SB and SB because PMOS transistors P12 and P13 coupled to SB and barSB are activated while the first sense amplifier 10B is deactivated. Under the multi-bit testing mode, the column selector selects simultaneously more than one, for example, two columns (e.g., YD0 and YDj), and complementary data signals will appear also as SB and SB.
Referring to FIG. 1B, the second sense amplifier 20 comprises a modified current mirror and receives the output signals from the first sense amplifiers 10A and 10B. Under the normal operating mode, since YD0 is selected, SA would be high, SA low, and SB and SB high. Then the second sense amplifier 20 outputs complementing data onto output lines OUT and OUT. That is, a high voltage is applied to the gate of NMOS transistors N1 and N2, which are serially connected to one another, thus allowing the currents to flow therethrough. That in turn activates the current mirror through PMOS transistors P1, P4 and P7.
Further, a low level voltage is applied to the gate of an NMOS transistor N7 and a high level voltage to an NMOS transistor N8, thus disallowing the currents to flow therethrough. In the end, the output line OUT outputs a high level voltage, while the output line OUT outputs a low level voltage. These output signals from the output lines OUT and OUT are provided to an output buffer.
Similarly, suppose that YDj associated with the first sense amplifier 10B is selected and the associated cell is initially set to a low value. Then, under the normal operating mode, SA and SA would be high, SB low, and SB high. Then a high voltage is applied to the gates of the NMOS transistors N7 and NS, which are connected in series with respect to one another, allowing the currents to flow therethrough. Consequently, the current mirror operation is performed through PMOS transistors P9, P3 and P6. Further, a low level voltage is applied to the gate of the NMOS transistor N2 and a high level voltage to the gate of the NMOS transistor N1, disallowing the currents to flow therethrough. Consequently, the output line OUT outputs a low level voltage, while the output line OUT outputs a high level voltage. Therefore, the status of SA, SA, SB and SB can be checked on the output lines OUT and OUT.
Under the multi-bit testing mode, two situations would exist. In the first situation, the first sense amplifiers 10A and 10B output identical data. For example, two identical high level signals appear as SA and SB and are applied to the second sense amplifier 20, while two identical low level signals appear as SA and SB and are applied to the second sense amplifier 20. In this situation, the second sense amplifier 20 operates much like when it is in the normal operating mode described above, and outputs normal data having a high or low signal level. In the second situation, the first sense amplifiers 10A and 10B output different data, which will be discussed more in detail below.
As indicated above, under the multi-bit testing mode, the column selector selects simultaneously more than one column, for example, one column from the columns YD0-YDi associated with the first sense amplifier 10A and another column from the columns YDj-YDn associated with the first sense amplifier 10B. One of SA and SA and one of SB and SB shall have a low signal level. One of two states "PASS" and "FAIL" is indicated based on the output which appears on the output lines OUT and OUT.
Under this circumstance, if the first sense amplifiers 10A and 10B output the same data (either same high or same low), PASS is indicated. For example, suppose that same high level signals appear as SA and SB and are applied to the second sense amplifier 20, while same low level signals appear as SA and SB. Then, the second sense amplifier 20 operates as in the normal operating mode, thereby outputting high and low signals as normal data on the output lines.
On the other hand, when the first sense amplifiers 10A and 10B output different data, FAIL is indicated. For example, suppose that SA is high; SA low; SB low; and SB high, then no currents will flow through NMOS transistor N1 and N2 which are serially connected one another, thereby deactivating the current mirror to operate through the PMOS transistor P1, P4 and P7. Further, no currents will flow through the serially connected NMOS transistor N7 and N8, thereby deactivating the current mirror to operate through the PMOS transistors P9, P3 and P6.
Moreover, since the NMOS transistors N3 and N6, which receive high voltage signals, are connected to the NMOS transistor N4 and N5 in series respectively, while the serially connected NMOS transistor N3 and N4 and the serially connected NMOS transistors N5 and N6 are connected in parallel with respect to one another, when the current flows through the NMOS transistors N3 and N6, the current mirror is allowed to operate through the PMOS transistors P5, P2 and P8. Consequently, both the outputs OUT and OUT of the second sense amplifier 20 become high, resulting in a high impedance on the output of the output buffer, thus indicating FAIL. Accordingly, the error status of the cells in the memory device is indicated.
As is apparent in the above description, the same circuit can operate both under the normal operating mode as well as the multi-bit testing mode. However, in such a multi-bit testing circuit for a semiconductor memory device, it is difficult to increase the number of the cells (or bits) to be tested; the number of bits that can be tested is limited. Further, when the signals which are applied to the second sense amplifier are weak, the operation of the current mirror circuit becomes unstable, resulting in incorrect output data and thus degrading the test accuracy.
Yet further, since the reliability of the multi-bit testing circuit relies on that of the operation of the current mirror circuit, and since the amount of the current flowing through the current mirror, when the current mirror is activated, can be varied, the operating speed of the circuit under the normal operating mode can be different from that under the multi-bit testing mode.